irfs11n50a, sihfs11n50a www.vishay.com vishay siliconix s13-1927-rev. e, 09-sep-13 1 document number: 91286 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet features ? low gate charge q g results in simple drive requirement ? improved gate, avalanche and dynamic dv/dt ruggedness ? fully characterize d capacitance and avalanche voltage and current ? effective c oss specified ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 note ? * this datasheet provides information about parts that are ? rohs-compliant and/or parts th at are non-rohs-compliant. for ? example, parts with lead (pb) te rminations are not rohs-compliant. ? please see the information/tables in this datasheet for details. applications ? switch mode power supply (smps) ? uninterruptible power supply ? high speed power switching typical smps topologies ? two transistor forward ? half and full bridge ? power factor correction boost note a. see device orientation. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 4.5 mh, r g = 25 ? , i as = 11 a (see fig. 12). c. i sd ? 11 a, di/dt ? 140 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. product summary v ds (v) 500 r ds(on) ( ? )v gs = 10 v 0.52 q g (max.) (nc) 52 q gs (nc) 13 q gd (nc) 18 configuration single n-channel mosfet g d s d 2 pak (to-263) g d s available available ordering information package d 2 pak (to-263) d 2 pak (to-263) d 2 pak (to-263) lead (pb)-free and halogen-free sihfs11n50a-ge3 sihfs11n50atrr-ge3 a sihfs11n50atrl-ge3 a lead (pb)-free irfs 11n50apbf irfs11n50atrrp a irfs11n50atrlp a absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 continuous drain current v gs at 10 v t c = 25 c i d 11 a t c = 100 c 7.0 pulsed drain current a i dm 44 linear derating factor 1.3 w/c single pulse avalanche energy b e as 275 mj repetitive avalanche current a i ar 11 a repetitive avalanche energy a e ar 17 mj maximum power dissipation t c = 25 c p d 170 w peak diode recovery dv/dt c dv/dt 6.9 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) d for 10 s 300
irfs11n50a, sihfs11n50a www.vishay.com vishay siliconix s13-1927-rev. e, 09-sep-13 2 document number: 91286 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width ? 300 s; duty cycle ? 2 %. c. c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising fom 0 % v ds to 80 % v ds . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-case (drain) r thjc -0.75 c/w case-to-sink, flat, greased surface r thcs 0.50 - maximum junction-to-ambient r thja -62 specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0, i d = 250 a 500 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma -0.060- v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v - - 25 a v ds = 400 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-sta te resistance r ds(on) v gs = 10 v i d = 6.6 a b - - 0.52 ? forward transconductance g fs v ds = 50 v, i d = 6.6 a 6.1 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 1423 - pf output capacitance c oss - 208 - reverse transfer capacitance c rss -8.1- output capacitance c oss v gs = 0 v v ds = 1.0 v, f = 1.0 mhz - 2000 - v ds = 400 v, f = 1.0 mhz - 55 - effective output capacitance c oss eff. v ds = 0 v to 400 v c -97- total gate charge q g v gs = 10 v i d = 11 a, v ds = 400 v see fig. 6 and 13 b --52 nc gate-source charge q gs --13 gate-drain charge q gd --18 turn-on delay time t d(on) v dd = 250 v, i d = 11 a r g = 9.1 ? , r d = 22 ??? see fig. 10 b -14- ns rise time t r -35- turn-off delay time t d(off) -32- fall time t f -28- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol ? showing the ? integral reverse ? p - n junction diode --11 a pulsed diode forward current a i sm --44 body diode voltage v sd t j = 25 c, i s = 11 a, v gs = 0 v b --1.5v body diode reverse recovery time t rr t j = 25 c, i f = 11 a, di/dt = 100 a/s b - 510 770 ns body diode reverse recovery charge q rr -3.45.1c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) s d g
irfs11n50a, sihfs11n50a www.vishay.com vishay siliconix s13-1927-rev. e, 09-sep-13 3 document number: 91286 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature
irfs11n50a, sihfs11n50a www.vishay.com vishay siliconix s13-1927-rev. e, 09-sep-13 4 document number: 91286 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
irfs11n50a, sihfs11n50a www.vishay.com vishay siliconix s13-1927-rev. e, 09-sep-13 5 document number: 91286 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 9 - maximum drain curre nt vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f a r g i as 0.01 t p d.u.t. l v ds + - v dd driver 15 v 20 v i as v ds t p
irfs11n50a, sihfs11n50a www.vishay.com vishay siliconix s13-1927-rev. e, 09-sep-13 6 document number: 91286 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 12d - typical drain-to-source voltage vs. avalanche current fig. 13b - gate ch arge test circuit q gs q gd q g v g charge v gs d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
irfs11n50a, sihfs11n50a www.vishay.com vishay siliconix s13-1927-rev. e, 09-sep-13 7 document number: 91286 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 14 - for n-channel ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91286 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
document number: 91364 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-263ab (high voltage) notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimensions are shown in millimeters (inches). 3. dimension d and e do not include mold flash. mold flash shal l not exceed 0.127 mm (0.005") per side. these dimensions are me asured at the outmost extremes of the plastic body at datum a. 4. thermal pad contour optional within dimension e, l1, d1 and e1. 5. dimension b1 and c1 apply to base metal only. 6. datum a and b to be determined at datum plane h. 7. outline conforms to jedec outline to to-263ab. 5 4 1 3 l1 l2 d b b e h b a detail a a a c c2 a 2 x e 2 x b 2 2 x b 0.010 a b mm 0.004 b m base metal plating b 1, b 3 ( b , b 2) c1 (c) section b - b and c - c scale: none lead tip 4 34 (dat u m a) 2 c c b b 5 5 v ie w a - a e1 d1 e 4 4 b h seating plane ga u ge plane 0 to 8 detail ?a? rotated 90 cw scale 8 :1 l3 a1 l4 l millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 4.06 4.83 0.160 0.190 d1 6.86 - 0.270 - a1 0.00 0.25 0.000 0.010 e 9.65 10.67 0.380 0.420 b 0.51 0.99 0.020 0.039 e1 6.22 - 0.245 - b1 0.51 0.89 0.020 0.035 e 2.54 bsc 0.100 bsc b2 1.14 1.78 0.045 0.070 h 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 l 1.78 2.79 0.070 0.110 c 0.38 0.74 0.015 0.029 l1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 l2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 l3 0.25 bsc 0.010 bsc d 8.38 9.65 0.330 0.380 l4 4.78 5.28 0.188 0.208 ecn: s-82110-rev. a, 15-sep-08 d w g: 5970
an826 vishay siliconix document number: 73397 11-apr-05 www.vishay.com 1 recommended minimum pads for d 2 pak: 3-lead 0.635 (16.129) recommended minimum pads dimensions in inches/(mm) 0.420 (10.668) 0.355 (9.017) 0.145 (3.683) 0.135 (3.429) 0.200 (5.080) 0.050 (1.257) return to index
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